Memory systems have significantly evolved due to advancements in fabrication technology. High-Bandwidth-Memory (HBM) is an example of an emerging memory standard defined by the JEDEC organization. HBM is a high-performance dynamic random access memory (DRAM) that uses a wide-interface architecture and stacked configurations to achieve high-speed and low-power operation. The HBM subsystems involve different types of memory controllers (e.g., full-speed or half-speed), HBM mixed-signal physical interface (PHY) and HBM DRAM. The HBM subsystem is especially suitable for applications involving high performance graphics and computing, high-end networking and communication devices, and memory-hungry processors.
In general, the HBM operates in either normal operation or low power mode. During normal operation mode, the PHY control slice and PHY data slice are both used to transfer control commands and data between the Memory Controller and HBM DRAM devices. During the conventional low power mode, the Memory Controller allows the PHY to enter into a low power mode through the Low Power Control Interface only when the DRAM devices have entered into a Power Down (PD) or Self-Refresh (SREF) state. In the PD and SREF mode of HBM DRAM device, the Memory Controller may direct the PHY to shut down its control slice and data slice because there are no commands and no data transmissions between Memory Controller and PHY.
In a HBM subsystem, it is advantageous to conserve power consumption by placing the PHY in a low power state when idle. The PHY is considered idle when the control interface is not sending any commands and all read and write data has transferred on the PHY, reached its destination, and the write data transfer has completed on the DRAM bus. For example, the PHY may enter a lower power state when the Memory Controller is aware that the memory devices will remain in an idle state for a period of time. Frequently used HBM commands (e.g., PREA, REF, etc.) contain timing windows when no data transmission occurs on DFI data signals between Memory Controller and PHY data slice. As such, these windows may be utilized to power down the data path through a low power control handshake. Depending on the state of the subsystem, the Memory Controller will communicate this information to the PHY allowing the PHY to enter the appropriate power saving state.
One mechanism for addressing wasteful power consumption is to set idle memory in a low power mode. However, it can be difficult to know when to transition in and out of low power mode because there are latencies associated with entering into and exiting from the various operation modes. A policy that toggles modes too frequently may increase the latency of memory commands which thereby reduces performance. Additionally, a policy that transitions to low power mode too slowly will miss opportunities to save power, while a policy that transitions out of low power mode too slowly will unnecessarily degrade performance.
Therefore, there is a need for an improved approach to using a command-oriented method to shutting down the data slice during an idle period based on different command types.